This application claims priority from Korean Application No. 2001-15717, filed Mar. 26, 2001, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to integrated circuit devices and methods for manufacturing the same.
Various integrated circuit devices, including semiconductor memory devices such as DRAMs, include a resistor pattern. For example, a resistor pattern may be provided having a resistance chosen to control a signal transmission characteristic of the integrated circuit device. The resistor pattern may be formed, for example, using a polysilicon layer having a specific resistance of thousands of microohms (xcexcxcexa9) per centimeter (cm) (xcexcxcexa9xc2x7cm).
The resistor pattern for a semiconductor memory device, such as a DRAM, may be formed in a circuit including a capacitor. The resistor pattern may be formed by patterning an upper capacitor electrode material layer and a doped polysilicon layer, which are sequentially stacked on a substrate of the device, using a single mask before a metal conductive line is formed. Such an approach may be used as it is generally relatively easy to control a thickness of the polysilicon layer to control the resistance value of the resistor pattern. Furthermore, the resistor pattern is typically formed after a high temperature heating process that also may affect the resistance value of the resistor pattern.
However, a problem may arise where the upper capacitor electrode is a low resistance material, such as a material having a specific resistance of several xcexcxcexa9xc2x7cm up to hundreds of xcexcxcexa9xc2x7cm. Examples of such materials include ruthenium (Ru), platinum (Pt), and the like. Where such a material is present, its low resistivity characteristics may limit the ability to provide a desired resistance value for the resistor pattern. To form a resistor pattern having a desired resistance value, the resistor pattern may have to be formed with a relatively thin thickness or with a relatively long length to provide a desired resistance given the low specific resistance of the material. Therefore, it is generally not possible to simultaneously form such an upper capacitor electrode and a polysilicon layer providing sufficient resistance.
An example of a resistor pattern for use in a conventional semiconductor memory device will now be described with reference to the cross-sectional view of FIG. 1. As shown in FIG. 1, an upper capacitor electrode 11, having a relatively low resistance value, is formed on a semiconductor substrate 10. A doped polysilicon layer 12 is formed on the other side of the upper capacitor electrode 11. The polysilicon layer 12 can have a structure including a barrier metal of, for example, titanium nitride (TiN). As discussed above, the upper capacitor electrode 11 may be, for example, Ru or Pt. Thus, the resistor pattern in such a configuration may have the following structure: Ru/polysilicon, Pt/polysilicon, Ru/TiN/polysilcon, and/or Pt/TiN/polysilicon.
In such a conventional resistor pattern, because the doped polysilicon layer 12 is formed on an upper capacitor electrode 11 that has a relatively low resistance value (compared to the doped polysilicon layer 12), an electrical current passing through the resistor pattern may substantially flow to the upper capacitor electrode 11 because of its relatively low resistance value. Thus, the ability to increase the resistance value of the resistor pattern based on the resistivity of the higher resistance value polysilicon layer 12 may be very limited. To avoid this problem, the doped polysilicon layer is generally not formed using the same mask as used to form the lower resistivity upper capacitor electrode 11.
Embodiments of the present invention include methods for forming an integrated circuit device including a resistor pattern having a desired resistance value. A low resistive layer is formed on an integrated circuit substrate. An insulating layer is formed on the low resistive layer opposite the integrated circuit substrate. A high resistive layer, which may have a specific resistance of at least about a hundred xcexcxcexa9xc2x7cm, is formed on the insulating layer opposite the low resistive layer. The low resistive layer, the insulating layer and the high resistive layer define the resistor pattern in a region of the integrated circuit substrate.
In other embodiments of the present invention, the integrated circuit device is an integrated circuit memory device including a capacitor and wherein the step of forming a low resistive layer comprises concurrently forming the low resistive layer defining the resistor pattern in the region of the integrated circuit substrate and forming an upper capacitor electrode of the capacitor in a different region of the integrated circuit substrate, wherein the low resistive layer defining the resistor pattern and the upper capacitor electrode are formed of the same material.
The low resistive layer may be at least one of ruthenium (Ru), platinum (Pt), RuO2, Ir, IrO2, W, aluminum (Al), Cu, titanium nitride (TiN), tantalum nitride (TaN) and/or WN and the high resistive layer may be a doped polysilicon. The insulating layer may be at least one of SiO2, Ta2O5, Al2O3 and/or Si3N4.
In further embodiments of the present invention, at least one of a source and/or a drain is formed in a cell region of the integrated circuit memory device between the region of the integrated circuit substrate including the resistor pattern and the different region of the integrated circuit substrate including the capacitor. A first metal contact, having a first depth, may be formed to the upper capacitor electrode and a second metal contact, having a second depth different from the first depth, may be formed to the high resistive layer of the resistor pattern. A titanium nitride (TiN) layer may be formed between the low resistive layer and the insulating layer.
In other embodiments of the present invention, methods are provided for forming an integrated circuit device including a resistor pattern having a desired resistance value. An integrated surface substrate is provided and a low resistive layer is formed defining an upper capacitor electrode in a first region of the integrated circuit substrate and a low resistive layer of the resistor pattern in a second region of the integrated circuit substrate displaced from the first region. An insulating layer is formed on the upper capacitor electrode and on the low resistive layer of the resistor pattern opposite the integrated circuit substrate. A high resistive layer is formed on the insulating layer on the upper capacitor electrode and on the low resistive layer of the resistor pattern opposite the low resistive layer. The low resistive layer, the insulating layer and the high resistive layer are formed through a single photolithography process using a common mask.
The high resistive layer may have a specific resistance of at least about a hundred xcexcxcexa9xc2x7cm. A metal contact may be formed to the upper capacitor electrode and a metal contact may be formed to the high resistive layer of the resistor pattern using a two photo mask process. The integrated circuit device may be an integrated circuit memory device having a junction region and the two photo mask process may further include forming a metal contact to the junction region.
In further embodiments of the present invention, the steps of forming the low resistive layer, the insulating layer and the high resistive layer may include depositing the low resistive layer over the entire surface of at least a portion of the integrated circuit substrate including the first region and the second region. The insulating layer may be deposited on the low resistive layer and the high resistive layer deposited on the insulating layer. The low resistive layer, the insulating layer and the high resistive layer may then be patterned to form the upper capacitor electrode in the first region and the resistor pattern in the second region of the integrated circuit substrate. The integrated circuit device may be an integrated circuit memory device and the first region may be a cell region of the integrated circuit memory device and the second region may be a periphery region of the integrated circuit memory device.
In other embodiments of the present invention, resistor patterns are provided for an integrated circuit memory device having a capacitor. The resistor patterns include an integrated circuit substrate and a low resistive layer formed on the integrated circuit substrate. The low resistive layer defines an upper capacitor electrode of the capacitor and a low resistive layer of the resistor pattern in a region of the integrated circuit substrate displaced from the upper capacitor electrode. An insulating layer is formed on the upper capacitor electrode and the low resistive layer of the resistor pattern. A high resistive layer is formed on the insulating layer. The low resistive layer, the insulating layer and the high resistive layer define the resistor pattern in the region of the integrated circuit substrate displaced from the upper capacitor electrode. In various embodiments, the high resistive layer has a specific resistance of at least a hundred xcexcxcexa9xc2x7cm or of at least a thousand xcexcxcexa9xc2x7cm. The high resistive layer may be a doped polysilicon layer.
In further embodiments of the present invention, methods are provided of forming a resistor pattern in a semiconductor memory device having a capacitor. An integrated circuit substrate is provided including a cell region and a periphery region, the cell region including a first cell region and a second cell region. A low resistive material layer is deposited over all of a region of the semiconductor substrate including the cell region and the periphery region. An insulating material layer is deposited on the low resistive material layer and a high resistive material layer is deposited on the insulating layer. The low resistive material layer, the insulating material layer and the high resistive material layer are patterned to form a low resistive layer, an insulating layer and a high resistive layer, respectively, over the first cell region and the periphery region of the integrated circuit substrate. A TiN layer may also be deposited on the low resistive layer and an under insulating layer may be formed on the entire surface of the integrated circuit substrate.
In yet further embodiments of the present invention, methods of forming metal contacts of a resistor pattern for use in an integrated circuit memory device having a capacitor are provided. An integrated circuit substrate is provided. The integrated circuit substrate includes a cell region and a periphery region. The cell region includes a first cell region and a second cell region. The first cell region includes a first low resistive layer, a first insulating layer and a first high resistive layer that are sequentially stacked. The second cell region includes a conductive layer. The periphery region includes the resistor pattern. The resistor pattern includes a second low resistive layer, a second insulating layer and a second high resistive layer that are sequentially stacked. A planarization layer is formed over all of a surface of the integrated circuit substrate in at least a region including the cell region and the periphery region. First to third metal contacts are formed. The first metal contact is formed in the first cell region and exposes a portion of the first low resistive layer. The second metal contact is formed in the second cell region and exposes a portion of the conductive layer. The third metal contact is formed in the periphery region and exposes a portion of the second high resistive layer. The first metal contact may be formed using a first mask and the second metal contact and the third metal contact may be formed using a second mask. In alternative embodiments, the first metal contact and the second metal contact may be formed using a first mask and the third metal contact may be formed using a second mask.